Intel 440BX Dual CPU free download

File name 440BX Dual CPU.pdf

A B C D E 4 Intel 100 MHz Pentium(tm) II processor/440BX AGPset Dual Processor Customer Reference Schematics Revision 1.0 TITLE COVER SHEET BLOCK DIAGRAM SLOT 1 CONNECTOR CLK SYNTHESIZER 82443BX FET SWITCHES DIMM SOCKETS 4 PAGE 1 2 3,4,5,6 7 8,9,10 11,12 13,14,15,16 17.18 19 20 21 22,23 24 25 26 27 28 29 30 31 32 33 34 35 INTEL CORPORATION ** Please note that these schematics are subject to change. THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not infringe such rights. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. *Third-party brands and names are the property of their respective owners. Copyright * Intel Corporation 1997, 1998 3 3 PIIX4E IOAPIC ULTRA I/O AGP CONNECTOR PCI CONNECTORS ISA CONNECTORS IDE CONNECTORS USB CONNECTORS FLASH BIOS 2 PARALLEL SERIAL/FLOPPY KEYBOARD/MOUSE VRM POWER CONNECTOR PROCESSOR BUS/CORE FREQ. PCI/AGP PULL-UPS & PULL-DOWNS ISA PULL-UPS 82443BX/DRAM DECOUPLING 2 36 37 38 Title PLATFORM COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-62 FOLSOM, CA 95630 1 1 BULK DECOUPLING TERMINATION DECOUPLING LM79 REVISION HISTORY 39 40 Intel Pentium(tm) II processor/440BX AGPset Dual Processor Cover Sheet S ize Custom Date: Document Number Intel(R) 440BX AGPset Thursday, April 09, 1998 D Rev 1.0 1 E Sheet of 40 A B C 1 2 3 4 5 6 7 8 APIC BUS VRM VTT GEN. PG. 31 A PENTIUM(tm) II Processor (SLOT 1) PG. 3,4 CK100 ITP CON. PG. 7 PENTIUM(tm) II Processor (SLOT 1) PG. 5,6 VRM VTT GEN. PG. 31 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AN END USER PRODUCT. iNTEL ISNOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION. & A MAX1617 ME PG. 3 MAX1617 ME PG. 5 DEVICE TABLE DEVICE TYPE FUSES ADDR SMBus Interface S Y S TEM BUS IOAPIC 82093AA PG. 19 AGP CONN. CNTL PG. 21 DATA ADDR ADDR/DATA CNTL AGP SIDEBAND ADDR S Y S T EM BUS CNTL CNTL DATA REFERENCE DESIGNATOR F1,F2,F3,F4 PAGE # 26,30 SMBus Interface Slot 1 Connectors ITP Connector DIMM Sockets J1A,B J2A,B J3 J4,J5,J6,J7 J8 J9,J10,J11,J12 J13, J14 J15, J16 J17,J18 J25,J26 3,4,5,6 82443BX 492 BGA PG. 8-10 CNTL DATA 13,14,15,16 21 22,23 35 25 26 31 B M E M O RY 4 SDRAM DIMM MODULES PG. 13-16 AGP Connector PCI Connector ISA Connector IDE Connect